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semiconductor group 1 4.98 hyb39s16400/800/160bt-8/-10 16mbit synchronous dram 16 mbit synchronous dram advanced information the hyb39s16400/800/160bt are dual bank synchronous dram s based on the die revisions d , & e and organized as 2 banks x 2mbit x4, 2 banks x 1mbit x8 and 2 banks x 512kbit x16 respectively. these synchronous devices achieve high speed data transfer rates up to 125 mhz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. the chip is fabricated with siemens advanced 16mbit dram process technology. the device is designed to comply with all jedec standards set for synchronous dram products, both electrically and mechanically. all of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. operating the two memory banks in an interleaved fashion allows random access operation to occur at higher rate than is possible with standard drams. a sequential and gapless data rate of up to 125 mhz is possible depending on burst length, cas latency and speed grade of the device. auto refresh (cbr) and self refresh operation are supported. these devices operate with a single 3.3v +/- 0.3v power supply and are available in tsopii packages. these synchronous dram devices are available with lv-ttl interfaces. ? high performance: ? fully synchronous to positive clock edge ? 0 to 70 c operating temperature ? dual banks controlled by a11 ( bank select) ? programmable cas latency : 2, 3 ? programmable wrap sequence : sequential or interleave ? programmable burst length: 1, 2, 4, 8 ? full page(optional) for sequencial wrap around -8 -10 units fck(max.) 125 100 mhz tck3 8 10 ns tac3 6 7 ns tck2 10 13.3 ns tac2 6 8 ns ? multiple burst read with single write operation ? automatic and controlled precharge command ? data mask for read / write control (x4, x8) ? dual data mask for byte control ( x16) ? auto refresh (cbr) and self refresh ? suspend mode and power down mode ? 4096 refresh cycles / 64 ms ? random column address every clk ( 1-n rule) ? single 3.3v +/- 0.3v power supply ? lvttl interface ? plastic packages: p-tsopi-44 400mil width ( x4, x8 ) p-tsopii -50 400 mil width ( x 16 ) ? -8 version for pc100 applications
semiconductor group 2 hyb39s16400/800/160bt-8/-10 16mbit synchronous dram ordering information pin description and pinouts: type ordering code package description lvttl-version: hyb 39s16400bt-8 p-tsopii-44 (400mil) 125mhz 2b x 2m x 4 sdram hyb 39s16400bt-10 p-tsopii-44-(400mil) 100mhz 2b x 2m x 4 sdram hyb 39s16800bt-8 p-tsopii-44-(400mil) 125mhz 2b x 1m x 8 sdram hyb 39s16800bt-10 p-tsopii-44 (400mil) 100mhz 2b x 1m x 8 sdram hyb 39s16160bt-8 p-tsopii-50 (400mil) 125mhz 2b x 512k x 16 sdram hyb 39s16160bt-10 p-tsopii-50-(400mil) 100mhz 2b x 512k x 16 sdram clk clock input dq data input /output cke clock enable dqm, ldqm, udqm data mask cs chip select vdd power (+3.3v) ras row address strobe vss ground cas column address strobe vddq power for dq s (+ 3.3v) we write enable vssq ground for dq s a0-a10 address inputs nc not connected a11 (bs) bank select
semiconductor group 3 hyb39s16400/800/160bt-8/-10 16mbit synchronous dram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 vdd nc vssq dq0 vddq nc vssq dq1 vddq nc nc we cas ras cs a11 a10 a0 a1 a2 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 vss nc vssq dq3 vddq nc vssq dq2 vddq nc nc dqm clk cke nc a9 a8 a7 a6 a5 21 22 44 43 42 41 a3 vdd a4 vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 vdd dq0 vssq dq1 vddq dq2 vssq dq3 vddq nc nc we cas ras cs a11 a10 a0 a1 a2 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 vss dq7 vssq dq6 vddq dq5 vssq dq4 vddq nc nc dqm clk cke nc a9 a8 a7 a6 a5 21 22 44 43 42 41 a3 vdd a4 vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 vdd dq0 dq1 vssq dq2 dq3 vddq dq4 dq5 vssq dq6 dq7 vddq ldqm we cas ras cs a11 a10 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 vss dq15 dq14 vssq dq13 dq12 vddq dq11 dq10 vssq dq9 dq8 vddq nc udqm clk cke nc a9 a8 21 22 44 43 42 41 a0 a1 a7 a6 23 24 25 50 49 48 47 46 45 a2 a3 vdd a5 a4 vss tsopii-44 2 bank x 2mbit x 4 hyb39s16400bt hyb39s16800bt 2 bank x 1mbit x 8 tsopii-44 ( 400 mil x 725 mil) ( 400 mil x 725 mil ) hyb39s16160bt 2 bank x 512kbit x 16 tsopii-50 ( 400 mil x 825 mil )
semiconductor group 4 hyb39s16400/800/160bt-8/-10 16mbit synchronous dram signal pin description pin type signal polarity function clk input pulse positive edge the system clock input. all of the sdram inputs are sampled on the rising edge of the clock. cke input level active high activates the clk signal when high and deactivates the clk signal when low, thereby inititiates either the power down mode, suspend mode or the self refresh mode. cs input pulse active low cs enables the command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. ras , cas we input pulse active low when sampled at the positive rising edge of the clock, cas , ras , and we define the command to be executed by the sdram. a0 - a10 input level during a bank activate command cycle, a0-a10 defines the row address (ra0-ra10) when sampled at the rising clock edge. during a read or write command cycle, a0-a9 defines the column address (ca0-can) when sampled at the rising clock edge.can depends from the sdram organisation. 4m x 4 sdram can = ca9 2m x 8 sdram can = ca8 1m x 16 sdram can = ca7 in addition to the column address, a10 is used to invoke autoprecharge operation at the end of the burst read or write cycle. if a10 is high, autoprecharge is selected and a11 defines the bank to be precharged (low=bank a, high=bank b). if a10 is low, autoprecharge is disabled. during a precharge command cycle, a10 is used in conjunction with a11 to control which bank(s) to precharge. if a10 is high, both bank a and bank b will be precharged regardless of the state of a11. if a10 is low, then a11 is used to define which bank to precharge. a11 (bs) input level selects which bank is to be active. a11 low selects bank a and a11 high selects bank b. dqx input output level data input/output pins operate in the same manner as on conventional drams. dqm ldqm udqm input pulse active high the data input/output mask places the dq buffers in a high impedance state when sampled high. in read mode, dqm has a latency of two clock cycles and controls the output buffers like an output enable. in write mode, dqm has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if dqm is high. vdd, vss supply power and ground for the input buffers and the core logic. vddq vssq supply isolated power supply and ground for the output buffers to provide improved noise immunity.
semiconductor group 5 hyb39s16400/800/160bt-8/-10 16mbit synchronous dram block diagram for hyb39s16400bt (2 banks x 4m x 4 sdram) data input/output buffers cke buffer clk buffer cs buffer ras buffer cas buffer we buffer dqm buffer cke clk cs ras cas dqm we command decoder mode register refresh clock row address counter self a1 a2 a3 a4 a5 a6 a7 a10 a8 a9 a0 a11 (bs) 12 12 2048 sequential control bank a row/column select bank a predecode a 8 data latches column decoder and dq gate sense amplifiers 1024 memory bank a 2048 x 1024 2048 row decoder 8 sequential control bank b predecode b 8 data latches column decoder and dq gate sense amplifiers 1024 memory bank b 2048 x 1024 2048 row decoder 8 address buffers (12) row/column select bank b 3 11 3 11 11 4 dq1 dq2 dq3 dq0
semiconductor group 6 hyb39s16400/800/160bt-8/-10 16mbit synchronous dram block diagram for hyb39s16800bt (2 banks x 1m x 8 sdram) dq0 data latches data latches 8 8 column decoder and dq gate sense amplifiers data input/output buffers 8 cke buffer clk buffer cs buffer ras buffer cas buffer we buffer dqm buffer cke clk cs ras cas dqm we command decoder mode register refresh clock row address counter self a1 a2 a3 a4 a5 a6 a7 a10 a8 a9 a0 a11 (bs) 12 12 sequential control bank a row/column select bank a predecode a column decoder and dq gate sense amplifiers sequential control bank b predecode b 8 address buffers (12) row/column select bank b 3 11 3 11 11 data latches 8 column decoder and dq gate sense amplifiers 512 memory bank b 2048 x 1024 memory bank b 2048 x 512 2048 row decoder row decoder 8 8 8 8 8 8 8 1024 512 memory bank a 2048 x 512 2048 row decoder row decoder dq1 dq2 dq3 dq4 dq5 dq6 dq7
semiconductor group 7 hyb39s16400/800/160bt-8/-10 16mbit synchronous dram block diagram for hyb39s16160bt (2 banks x 512k x 16 sdram) column decoder and dq gate sense amplifiers data latches data latches 8 8 column decoder and dq gate sense amplifiers column decoder and dq gate sense amplifiers 1024 512 memory bank a 2048 x 512 row decoder row decoder data latches data latches 8 8 column decoder and dq gate sense amplifiers 8 cke buffer clk buffer cs buffer ras buffer cas buffer we buffer dqm buffer cke clk cs ras cas udqm we command decoder mode register refresh clock row address counter self a1 a2 a3 a4 a5 a6 a7 a10 a8 a9 a0 a11 (bs) 12 12 sequential control bank a row/column select bank a predecode a column decoder and dq gate sense amplifiers sequential control bank b predecode b 8 address buffers (12) row/column select bank b 3 11 3 11 11 16 16 16 16 16 16 1024 256 memory bank a 2048 x 256 2048 row decoder row decoder data latches data latches 8 column decoder and dq gate sense amplifiers 256 memory bank b 2048 x 1024 memory bank b 2048 x 512 memory bank b 2048 x 1024 memory bank b 2048 x 256 2048 row decoder row decoder row decoder row decoder data input/output buffers dqm buffer ldqm 16 dq1 dq2 dq3 dq4 dq5 dq0 dq6 dq7 dq9 dq10 dq11 dq12 dq13 dq8 dq14 dq15
semiconductor group 8 hyb39s16400/800/160bt-8/-10 16mbit synchronous dram operation definition all of sdram operations are defined by states of control signals cs , ras , cas , we , and dqm at the positive edge of the clock. the following list shows the most important operation commands. mode register for application flexibility, a cas latency, a burst length, and a burst sequence can be programmed in the sdram mode register. the mode set operation must be done before any activate command after the initial power up. any content of the mode register can be altered by re- executing the mode set command. both banks must be in precharged state and cke must be high at least one clock before the mode set operation. after the mode register is set, a standby or nop command is required. low signals of ras , cas , and we at the positive edge of the clock activate the mode set operation. address input data at this timing defines parameters to be set as shown in the following table. operation cs ras cas we (l/u)dqm standby, ignore ras , cas , we and address h x x x x row address strobe and activating a bank l l h h x column address strobe and read command l h l h x column address strobe and write command l h l l x precharge command l l h l x burst stop command l h h l x self refresh entry l l l h x mode register set command l l l l x write enable/output enable x x x x l write inhibit/output disable x x x x h no operation (nop) l h h h x
semiconductor group 9 hyb39s16400/800/160bt-8/-10 16mbit synchronous dram address input for mode set (mode register operation) sequential burst addressing interleave burst addressing 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0 bs a3 a4 a2 a1 a0 a10 a9 a8 a7 a6 a5 address bus (ax) bt burst length cas latency mode register (mx) cas latency m6 m5 m4 latency 0 0 0 reserve 001 1 010 2 011 3 1 0 0 reserve 1 0 1 reserve 1 1 0 reserve 1 1 1 reserve burst length m2 m1 m0 length sequential interleave 000 1 1 001 2 2 010 4 4 011 8 8 1 0 0 reserve reserve 1 0 1 reserve reserve 1 1 0 reserve reserve 1 1 1 full page*) reserve burst type m3 type 0 sequential 1 interleave operation mode m11 m10 m9 m8 m7 mode 0 0 0 0 0 normal x x 100 multiple burst with single write operation mode *) optional
semiconductor group 10 hyb39s16400/800/160bt-8/-10 16mbit synchronous dram read and write access mode when ras is low and both cas and we are high at the positive edge of the clock, a ras cycle starts. according to address data, a word line of the selected bank is activated and all of sense amplifiers associated to the word line are fired. a cas cycle is triggered by setting ras high and cas low at a clock timing after a necessary delay, trcd, from the ras timing. we is used to define either a read (we = h) or a write (we = l) at this stage. sdram provides a wide variety of fast access modes. in a single cas cycle, serial data read or write operations are allowed at up to a 125 mhz data rate. the numbers of serial data bits are the burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8 and full page, where full page is an optional feature in this device. column addresses are segmented by the burst length and serial data accesses are done within this boundary. the first column address to be accessed is supplied at the cas timing and the subsequent addresses are generated automatically by the programmed burst length and its sequence. for example, in a burst length of 8 with interleave sequence, if the first address is 2 , then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5 . full page burst operation is only possible using the sequential burst type and page length is a function of the i/o organisation and column addressing. full page burst operation do not self terminate once the burst length has been reached. in other words, unlike burst length of 2, 3 or 8, full page burst continues until it is terminated using another command. similar to the page mode of conventional dram s, burst read or write accesses on any column address are possible once the ras cycle latches sense amplifiers. the maximum tras or the refresh interval time limits the number of random column accesses. a new burst access can be done even before the previous burst ends. the interrupt operation at every clock cycles is supported. when the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. an interrupt which accompanies with an operation change from a read to a write is possible by exploiting dqm to avoid bus contention. when two banks are activated sequentially, interleaved bank read or write operations are possible. with the programmed burst length, alternate access and precharge operations on two banks can realize fast serial data access modes among many different pages. once two banks are activated, column to column interleave operation can be done between two different pages. refresh mode sdram has two refresh modes, a cas before ras (cbr) automatic refresh and a self refresh. all of banks must be precharged before applying any refresh mode. an on-chip address counter increments the word and the bank addresses and no bank information is required for both refresh modes. the chip enters the automatic refresh mode, when ras and cas are held low and cke and we are held high at a clock timing. the mode restores word line after the refresh and no external precharge command is necessary. a minimum trc time is required between two automatic refreshes in a burst refresh mode. the same rule applies to any access command after the automatic refresh operation. the chip has an on-chip timer and the self refresh mode is available. it enters the mode when ras , cas , and cke are low and we is high at a clock timing. all of external control signals including the clock are disabled. returning cke to high enables the clock and initiates the refresh exit operation. after the exit command, at least one trc delay is required prior to any access command.
semiconductor group 11 hyb39s16400/800/160bt-8/-10 16mbit synchronous dram dqm function dqm has two functions for data i/o read write operations. during reads, when it turns to high at a clock timing, data outputs are disabled and become high impedance after two clock delay (dqm data disable latency t dqz ). it also provides a data mask function for writes. when dqm is activated, the write operation at the next clock is prohibited (dqm write mask latency t dqw = zero clocks). suspend mode during normal access mode, cke is held high and clk is enabled. when cke is low, it freezes the internal clock and extends data read and write operations. one clock delay is required for mode entry and exit (clock suspend latency t csl ). power down in order to reduce standby power consumption, a power down mode is available. bringing cke low enters the power down mode and all of receiver circuits are gated. all banks must be precharged before entering this mode. one clock delay is required for mode entry and exit. the power down mode does not perform any refresh operation. auto precharge two methods are available to precharge sdrams. in an automatic precharge mode, the cas timing accepts one extra address, ca10, to determine whether the chip restores or not after the operation. if ca10 is high when a read command is issued, the read with auto-precharge function is initiated. the sdram automatically enters the precharge operation one clock after the read command is registered for cas latencies of 1 and 2, and two clocks for cas latencies of 3. if cas10 is high when a write command is issued, the write with auto-precharge function is initiated. the sdram automatically enters the precharge operation one clock delay form the last data-in for cas latencies of 1 and 2 and two clocks for cas latencies of 3. this delay is referenced as t dpl . precharge command if ca10 is low, the chip needs another way to precharge. in this mode, a separate precharge command is necessary. when ras and we are low and cas is high at a clock timing, it triggers the precharge operation. two address bits, a10 and a11, are used to define banks as shown in the following list. the precharge command may be applied coincident with the last of burst reads for cas latency = 1 and with the second to the last read data for cas latencies = 2 & 3. writes require a time t dpl from the last burst data to apply the precharge command. bank selection by address bits a10 a11 bank a only low low bank b only low high both a and b high don t care
semiconductor group 12 hyb39s16400/800/160bt-8/-10 16mbit synchronous dram burst termination once a burst read or write operation has been initiated, there are several methods in which to terminate the burst operation prematurely. these methods include using another read or write command to interrupt an existing burst operation, use a precharge command to interrupt a burst cycle and close the active bank, or using the burst stop command to terminate the existing burst operation but leave the bank open for future read or write commands to the same page of the active bank. when interrupting a burst with another read or write command care must be taken to avoid dq contention. the burst stop command, however, has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. if a burst stop command is issued during a burst write operation, then any residual data from the burst write cycle will be ignored. data that is presented on the dq pins before the burst stop command is registered will be written to the memory. power up procedure all vdd and vddq must reach the specified voltage no later than any of input signal voltages. an initial pause of 200 m sec is required after power on. all banks have to be precharged and a minimum of 2 auto-refresh cycles are required prior to the mode register set operation.
semiconductor group 13 hyb39s16400/800/160bt-8/-10 16mbit synchronous dram absolute maximum ratings operating temperature range ......................................................................................... 0 to + 70 c storage temperature range...................................................................................... C 55 to + 150 c input/output voltage .............................................................................. C 0.5 to min(vcc+0.5, 4.6) v power supply voltage vdd / vddq.......................................................................... C 1.0 to + 4.6 v power dissipation............................................. ............................................................... . ..........1 w data out current (short circuit) ............................................................................................... . 50 ma note: stresses above those listed under absolute maximum ratings may cause permanent damage of the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operation and characteristics for lv-ttl versions: t a = 0 to 70 c; v ss = 0 v; v dd, v ddq = 3.3 v 0.3 v notes: 1. all voltages are referenced to vss. 2. vih may overshoot to vcc + 2.0 v for pulse width of < 4ns with 3.3v. vil may undershoot to -2.0 v for pulse width < 4.0 ns with 3.3v. pulse width measured at 50% points with amplitude measured peak to dc reference. capacitance t a = 0 to 70 c; v dd = 3.3 v 0.3 v, f = 1 mhz parameter symbol limit values unit notes min. max. input high voltage v i h 2.0 vcc+0.3 v 1, 2, 3 input low voltage v i l C 0.3 0.8 v 1, 2, 3 output high voltage ( i out = C 2.0 ma) v oh 2.4 C v 3 output low voltage ( i out = 2.0 ma) v ol C 0.4 v 3 input leakage current, any input (0 v < v i n < vddq, all other inputs = 0 v) i i (l) C 10 10 m a output leakage current (dq is disabled, 0 v < v out < v cc ) i o(l) C 10 10 m a parameter symbol values unit min. max. input capacitance (clk) c i 1 2.5 4.0 pf input capacitance (a0-a12, ba0,ba1,ras , cas , we , cs , cke, dqm) c i 2 2.5 5.0 pf input / output capacitance (dq) c i o 4.0 6.5 pf
semiconductor group 14 hyb39s16400/800/160bt-8/-10 16mbit synchronous dram operating currents (t a = 0 to 70 o c, vcc = 3.3v 0.3v (recommended operating conditions unless otherwise noted) notes: 1. the specified values are valid when addresses are changed no more than three times during trc(min.) and when no operation commands are registered on every rising clock edge during trc(min). 2. the specified values are valid when data inputs (dq s) are stable during trc(min.). parameter symbol test condition cas latency -8 -10 note max. max. operating current icc1 burst length = 4 trc>=trc (min.) tck>=tck(min.), io = 0ma 2 bank interleave operation 1 2 3 80 115 125 65 90 100 ma ma ma 1, 2 precharge standby current in power down mode icc2p cke<=vil(max), tck>=tck(min.) 33 ma icc2ps cke<=vil(max), tck=infinite 22ma precharge standby current in non-power down mode icc2n cke>=vih(min), tck>=tck(min.) input signals changed once in 3 cycles 20 20 ma cs = high icc2ns cke>=vih(min), tck=infinite, input signals are stable 10 10 ma active standby current in power down mode icc3p cke<=vil(max), tck>=tck(min.) 33ma icc3ps cke<=vil(max), tck=infinite, inpit signals are stable 22ma active standby current in non- power down mode icc3n cke>=vih(min), tck>=tck(min.), changed once in 3 cycles 25 25 ma cs = high, 1 icc3ns cke>=vih(min), tck=infinite, input signals are stable 15 15 ma burst operating current icc4 burst length = full page trc = infinite tck >= tck (min.), io = 0 ma 2 banks activated 1 2 3 50 80 120 40 65 95 ma 1, 2 auto (cbr) refresh current icc5 trc>=trc(min) 1 2 3 75 95 115 60 75 90 ma ma ma 1, 2 self refresh icc6 cke=<0,2v 11ma 1, 2 1
semiconductor group 15 hyb39s16400/800/160bt-8/-10 16mbit synchronous dram ac characteristics 1)2)3) t a = 0 to 70 c; v ss = 0 v; v cc = 3.3 v 0.3 v, t t = 1 ns parameter symbol limit values unit -8 -10 min max min max clock and clock enable clock cycle time cas latency = 3 cas latency = 2 t ck 8 10 C C 10 12 C C s ns ns clock frequency cas latency = 3 cas latency = 2 t ck C C 125 100 C C 100 75 mhz mhz access time from clock cas latency = 3 cas latency = 2 t ac C C 6 6 C C 7 8 ns ns 2, 4 clock high pulse width t ch 3C3Cns clock low pulse width t cl 3C3Cns transition time t t 0.5 10 0.5 10 ns setup and hold times input setup time t is 2C3Cns 5 input hold time t ih 1C1Cns 5 cke setup time t cks 2C3Cns 5 cke hold time t ckh 1C1Cns 5 mode register set-up time t rsc 16 C 20 C ns power down mode entry time t sb 08010ns common parameters row to column delay time t rcd 20 C 24 C ns 6 row active time t ras 45 100k 60 100k ns 6 row to column delay time t rcd 20 C 24 C ns 6 row precharge time t rp 20 C 24 C ns 6 row cycle time t rc 70 C 90 C ns 6 activate(a) to activate(b) command period t rrd 16 C 20 C ns 6
semiconductor group 16 hyb39s16400/800/160bt-8/-10 16mbit synchronous dram frequency vs. ac parameter relationship table: -8 -parts -10 -parts: cas (a) to cas (b) command period t ccd 1C1Cclk refresh cycle refresh period (4096 cycles) t ref C64C64ms self refresh exit time t srex 10 10 ns read cycle data out hold time t oh 3C3Cns2 data out to low impedance time t lz 0C0Cns data out to high impedance time t hz 38310ns 8 dqm data out disable latency t dqz 2C2Cclk write cycle write recovery time t wr 8C10Cns dqm write mask latency t dqw 0C0Cclk write latency t wl 0C0Cclk cl trc tras trp trrd trcd tccd t wl twr 125 mhz 3 9 6 3 2 3 1 0 1 100 mhz 2 7 5 2 2 2 1 0 1 cl trc tras trp trrd trcd tccd wl twr 100 mhz 3 8 6 3 2 3 1 0 1 75 mhz 2 7 5 2 2 2 1 0 1 parameter symbol limit values unit -8 -10 min max min max
semiconductor group 17 hyb39s16400/800/160bt-8/-10 16mbit synchronous dram notes for ac parameters: 1. for proper power-up see the operation section of this data sheet. 2. ac timing tests for lv-ttl versions have v il = 0.4 v and v ih = 2.4 v with the timing referenced to the 1.4 v crossover point. the transition time is measured between v ih and v il . all ac measurements assume t t =1ns with the ac output load circuit shown in fig.1. specified tac and toh parameters are measured with a 50 pf only, without any resistive termination and with a input signal of 1v / ns edge rate between 0.8v and 2.0 v. 3. if clock rising time is longer than 1 ns, a time (t t /2 - 0.5) ns has to be added to this parameter. 4. if tt is longer than 1 ns, a time (t t -1) ns has to be added to this parameter. 5. these parameter account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycle = specified value of timing period (counted in fractions as a whole number) self refresh exit is a synchronous operation and begins on the 2nd positive clock edge after cke returns high. self refresh exit is not complete until a time period equal to trc is satisfied once the self refresh exit command is registered. 1.4v 1.4v tsetup thold tac tac tlz toh thz clock input output 50 pf i/o z=50 ohm + 1.4 v 50 ohm 2.4 v 0.4 v t t fig.1 tch tcl 50 pf i/o measurement conditions for tac and toh
semiconductor group 18 hyb39s16400/800/160bt-8/-10 16mbit synchronous dram package outlines: tsop-44 (400).wmf glx05862 plastic package p-tsopii-44 ( 400mil, 0.8mm lead pitch) thin small outline package, smd plastic package p-tsopii-50 ( 400mil, 0.8mm lead pitch) 1) does not include plastic or metal protusion of 0.25 max. per side index marking 50 26 125 20.95 - +0.13 1) 0.5 11.76 10.16 +0.13 - +0.1 - - +0.2 0.15 +0.06 -0.03 0.8 0.4 -0.1 +0.05 0.2 50x 0.1 m 1.2 ma x 0.1 +0.05 - 1 +0.05 - thin small outline package, smd
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 19 timing diagrams 1. bank activate command cycle 2. burst read operation 3. read interrupted by a read 4. read to write interval 4.1 read to write interval 4.2 minimum read to write interval 4.3 non-minimum read to write interval 5. burst write operation 6. write and read interrupt 6.1 write interrupted by a write 6.2 write interrupted by read 7. burst read & write with auto-precharge 7.1 burst write with auto precharge 7.2 burst read with auto precharge 8. burst termination 8.1 termination of a burst read operation 8.2 termination of a burst write operation 9. ac- parameters 9.1 ac parameters for a write timing 9.2 ac parameters for a read timing 10. mode register set 11. power on sequence and auto refresh (cbr) 12. clock suspension (using cke) 12.1 clock suspension during burst read cas latency = 1 12. 2 clock suspension during burst read cas latency = 2 12. 3 clock suspension during burst read cas latency = 3 12. 4 clock suspension during burst write cas latency = 1 12. 5 clock suspension during burst write cas latency = 2 12. 6 clock suspension during burst write cas latency = 3 13. power down mode and clock suspend 14. auto refresh (cbr) 15. self refresh ( entry and exit) 16. random column read ( page within same bank) 16.1 cas latency = 1 16.2 cas latency = 2 16.3 cas latency = 3 17. random column write ( page within same bank) 17.1 cas latency = 1 17.2 cas latency = 2 17.3 cas latency = 3
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 20 timing diagrams (cont d) 18. random row read ( interleaving banks) 18.1 cas latency = 1 18.2 cas latency = 2 18.3 cas latency = 3 19. random row write ( interleaving banks) 19.1 cas latency = 1 19.2 cas latency = 2 19.3 cas latency = 3 20. full page read cycle (optional feature) 20.1 cas latency = 1 20.2 cas latency = 2 20.3 cas latency = 3 21. full page write cycle (optional feature) 21.1 cas latency = 1 21.2 cas latency = 2 21.3 cas latency = 3 22. precharge termination of a burst 22.1 cas latency = 1 22.2 cas latency = 2 22.3 cas latency = 3
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 21 1. bank activate command cycle (cas latency = 3) 2. burst read operation (burst length = 4, cas latency = 1, 2, 3) address clk t0 t t1 t t t t command nop nop nop bank a row addr. bank a activate write a with auto bank a col. addr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bank b activate bank a row addr. bank a activate t rcd : h o r l t rc precharge t rrd bank b row addr. command read a nop nop nop nop nop nop nop dout a 0 cas latency = 1 t ck2, dq s cas latency = 2 t ck3, dq s cas latency = 3 dout a 1 dout a 2 dout a 3 nop clk t0 t2 t1 t3 t4 t5 t6 t7 t8 t ck1, dq s dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 22 3. read interrupted by a read (burst length = 4, cas latency = 1, 2, 3) 4.1 read to write interval (burst length = 4, cas latency = 3) command read a read b nop nop nop nop nop nop t ck1, dq s cas latency = 1 t ck2, dq s cas latency = 2 t ck3, dq s cas latency = 3 nop clk t0 t2 t1 t3 t4 t5 t6 t7 t8 dout b 0 dout b 1 dout b 2 dout b 3 dout a 0 dout b 0 dout b 1 dout b 2 dout b 3 dout a 0 dout b 0 dout b 1 dout b 2 dout b 3 dout a 0 command nop read a nop nop nop nop write b nop nop dqm dout a 0 din b 0 din b 1 din b 2 : h or l must be hi-z before the write command dq s minimum delay between the read and write commands = 4+1 = 5 cycles clk t0 t2 t1 t3 t4 t5 t6 t7 t8 t dqz t dqw
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 23 4 2. minimum read to write interval (burst length = 4, cas latency = 1, 2) 4. 3. non-minimum read to write interval (burst length = 4, cas latency = 3 command nop bank a nop read a write a nop nop nop dqm din a 0 din a 1 din a 2 din a 3 : h or l din a 0 din a 1 din a 2 din a 3 must be hi-z before the write command t ck1, dq s cas latency = 1 t ck2, dq s cas latency = 2 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 nop activate 1 clk interval t dqz t dqw nop read a nop nop read a nop write b nop nop dqm din b 0 din b 1 din b 2 : h o r l t ck1, dq s cas latency = 1 t ck2, dq s cas latency = 2 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a 1 dout a 0 dout a 0 din b 0 din b 1 din b 2 command din b 0 din b 1 din b 2 dout a 2 dout a 1 dout a 0 must be hi-z before the write command t ck3, dq s cas latency = 3 t dqz t dqw
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 24 5. burst write operation (burst length = 4, cas latency = 1, 2, or 3) 6.1 write interrupted by a write (burst length = 4, cas latency = 1, 2, or 3) command nop write a nop nop nop nop nop nop dq s din a 0 din a 1 din a 2 din a 3 nop clk t0 t2 t1 t3 t4 t5 t6 t7 t8 extra data is ignored after the first data element and the write are registered on the same clock edge. don t care termination of a burst. command nop write a write b nop nop nop nop nop dq s din a 0 din b 0 din b 1 din b 2 nop din b 3 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 1 clk interval
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 25 6.2 write interrupted by a read (burst length = 4, cas latency = 1, 2, 3) 7.1 burst write with auto-precharge burst length = 2, cas latency = 1, 2, 3) c ommand nop write a read b nop nop nop nop nop nop t ck1, dq s c as latency = 1 din a 0 t ck2, dq s c as latency = 2 din a 0 t ck3, dq s c as latency = 3 din a 0 c lk t0 t2 t1 t3 t4 t5 t6 t7 t8 input data for the write is ignored. input data must be removed from the dq s at least one clock cycle before the read dataappears on the outputs to avoid data contention. don t care don t care don t care dout b 0 dout b 1 dout b 2 dout b 3 dout b 0 dout b 1 dout b 2 dout b 3 dout b 0 dout b 1 dout b 2 dout b 3 command nop nop nop write a auto-precharge clk t0 t2 t1 t3 t4 t5 t6 t7 t8 nop bank a active nop nop din a 0 din a 1 din a 0 din a 1 * * dq s cas latency = 2 dq s cas latency = 3 begin autoprecharge bank can be reactivated after trp * t dpl t dpl t rp t rp din a 0 din a 1 t dpl t rp nop * dq s cas latency = 1
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 26 7.2 burst read with auto-precharge (burst length = 4, cas latency = 1, 2, 3) 8.1 termination of a burst read operation (cas latency = 1, 2, 3 / burst length = 8) command read a nop nop nop nop nop nop nop dout a 0 cas latency = 1 t ck2, dq s cas latency = 2 t ck3, dq s cas latency = 3 dout a 1 dout a 2 dout a 3 nop clk t0 t2 t1 t3 t4 t5 t6 t7 t8 t ck1, dq s dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 with ap begin autoprecharge bank can be reactivated after trp * * * * t rp t rp t rp command read a nop nop nop burst nop nop nop nop t ck1, dq s cas latency = 1 t ck2, dq s cas latency = 2 t ck3, dq s cas latency = 3 stop clk t0 t2 t1 t3 t4 t5 t6 t7 t8 the burst ends after a delay equal to the cas latency. dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 27 8.2 termination of a burst write operation (cas laency = 1, 2, 3, burst length = 8) command nop write a nop nop burst nop nop nop nop din a 0 din a 1 din a 2 stop clk t0 t2 t1 t3 t4 t5 t6 t7 t8 input data for the write is masked. dq s cas latency = 1,2,3 don t care
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 28 \ clk cke cs dq ras cas we ba dqm 9.1 ac parameters for write timing t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap burst length = 4, cas latency = 2 addr t cks t cs t ch t ckh t as t rcd t rc t rp t ds activate command bank a write with auto precharge command bank a activate command bank b write with auto precharge command bank b activate command bank a write command bank a precharge command bank a activate command bank a t dh ax0 ax3 ax2 ax1 bx0 bx3 bx2 bx1 ay0 ay3 ay2 ay1 t ck2 t ch t cl begin auto precharge bank a begin auto precharge bank b t dpl t rrd activate command bank b ray cbx ray ray rbx rbx cax rby rby raz raz rax rax t ah
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 29 \ clk cke cs dq ras cas we ba dqm 9.2 ac parameters for read timing t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t10 hi-z ap burst length = 2, cas latency = 2 addr t cs t ch t ckh t as t ah t rrd t rcd t ras t lz activate command bank a activate command bank b activate command bank a precharge command bank a t cks t ck2 ax0 ax1 read command bank a read with auto precharge command bank b t rc t rp t ac2 t ac2 t oh t hz t ch t cl bx0 begin auto precharge bank b bx1 t hz rbx ray rbx rbx ray cax rax rax
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 30 \ clk cke cs ras cas we ba 10. mode register set t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 ap addr precharge command all banks mode register set command any command address key 2 clock min.
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 31 \ clk cke cs dq ras cas we ba dqm 11. power on sequence and auto refresh (cbr) ttt t0 tt t tt t t t tt t1 tttt tt tt hi-z ap addr precharge command all banks t rp minimum of 2 refresh cycles are required 1st auto refresh command t rc high level is required 2nd auto refresh command inputs must be stable fo r 200 m s any command 2 clock min. mode register address key set command
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 32 \ clk cke cs dq ras cas we ba dqm 12.1 clock suspension during burst read (using cke) (1 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap burst length = 4, cas latency = 1 addr cax rax ax0 ax1 ax2 ax3 activate command bank a read command b a n k a clock suspend 2 cycles clock suspend 1 cycle clock suspend 3 cycles rax t hz t ck1
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 33 \ clk cke cs dq ras cas we ba dqm 12.2 clock suspension during burst read (using cke) (2 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap burst length = 4, cas latency = 2 addr cax rax ax0 ax1 ax2 ax3 activate command bank a clock suspend 2 cycles clock suspend 1 cycle clock suspend 3 cycles rax read command bank a t hz t ck2
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 34 \ clk cke cs dq ras cas we ba dqm 12.3 clock suspension during burst read (using cke) (3 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap burst length = 4, cas latency = 3 addr rax ax0 ax1 ax2 ax3 activate command bank a clock suspend 2 cycles clock suspend 1 cycle clock suspend 3 cycles rax read command bank a cax t hz t ck3
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 35 \ clk cke cs dq ras cas we ba dqm 12.4 clock suspension during burst write (using cke) (1 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap burst length = 4, cas latency = 1 addr cax rax activate command bank a write command b a n k a clock suspend 1 cycle clock suspend 2 cycles clock suspend 3 cycles dax3 dax2 dax0 dax1 rax t ck1
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 36 \ clk cke cs dq ras cas we ba dqm 12.5 clock suspension during burst write (using cke) (2 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap burst length = 4, cas latency = 2 addr cax rax activate command bank a rax dax0 clock suspend 1 cycle dax1 dax2 dax3 clock suspend 2 cycles clock suspend 3 cycles write command bank a t ck2
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 37 \ clk cke cs dq ras cas we ba dqm 12.6 clock suspension during burst write (using cke) (3 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap burst length = 4, cas latency = 3 addr rax activate command bank a rax cax dax0 clock suspend 1 cycle dax1 dax2 dax3 clock suspend 2 cycles clock suspend 3 cycles write command bank a t ck3
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 38 \ clk cke cs dq ras cas we ba dqm 13. power down mode and clock suspend t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap burst length = 4, cas latency = 2 addr t cksp t cksp cax rax rax ax2 ax0 ax1 ax3 activate command bank a clock suspend mode entry clock suspend mode exit read command bank a clock mask start clock mask end precharge command bank a power down mode entry power down mode exit t hz any command t ck2
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 39 \ clk cke cs dq ras cas we ba dqm 14. auto refresh (cbr) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap addr ax0 ax1 burst length = 4, cas latency = 2 activate command read command precharge command auto refresh command auto refresh command t rc t rp t rc t ck2 all banks cax rax rax bank a bank a ax2 ax3 (minimum interval)
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 40 \ clk cke cs dq ras cas we a11(bs) dqm 15. self refresh (entry and exit) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t tt t10 t t tt tt t t hi-z a10 a0 - a9 all banks must be idle self refresh entry begin self refresh exit command t srex self refresh exit command issued self refresh exit t rc t cksr
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 41 \ clk cke cs dq ras cas we ba dqm 16.1 random column read (page within same bank) (1 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap burst length = 4, cas latency = 1 addr activate command bank a precharge command bank a caw raw raw cax read command bank a cay read command bank a activate command b a n k a raz caz read command bank a read command b a n k a raz aw0 aw1 aw2 aw3 ax0 ax1 ay0 ay1 az0 az1 az2 az3 ay2 ay3 t ck1
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 42 \ clk cke cs dq ras cas we ba dqm 16.2 random column read (page within same bank) (2 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap burst length = 4, cas latency = 2 addr activate command bank a cax read command bank a cay read command bank a aw0 aw1 aw2 aw3 ax0 ax1 ay0 ay1 az0 az1 az2 az3 ay2 ay3 caw read command bank a raw raw precharge command bank a activate command bank a caz read command bank a raz raz t ck2
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 43 \ clk cke cs dq ras cas we ba dqm 16.3 random column read (page within same bank) (3 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap burst length = 4, cas latency = 3 addr activate command bank a cax read command bank a cay read command bank a aw0 aw1 aw2 aw3 ax0 ax1 ay0 ay1 ay2 ay3 caw read command bank a raw raw precharge command bank a activate command bank a caz read command bank a raz raz t ck3
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 44 \ clk cke cs dq ras cas we ba dqm 17.1 random column write (page within same bank) (1 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap burst length = 4, cas latency = 1 addr rbw rbw cbw cbx activate command bank b write command bank b write command bank b cby write command bank b rbz rbz precharge command bank b activate command bank b cbz write command bank b dbw0 dbw3 dbw2 dbw1 dbx1 dbx0 dby0 dby3 dby2 dby1 dbz0 dbz3 dbz2 dbz1 t ck1
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 45 clk cke cs dq ras cas we a11(bs) dqm 18.1 random row read (interleaving banks) (1 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 8, cas latency = 1 a0 - a9 activate command bank b cbx rbx rbx cby read command bank b read command bank a read command bank b bx0 bx1 bx2 bx3 bx4 bx5 bx6 bx7 by0 by1 by2 t ck1 high t rcd t ac1 t rp cax rax rax rby rby activate command bank a precharge command bank b activate command bankb precharge command bank a ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 46 clk cke cs dq ras cas we a11(bs) dqm 18.2 random row read (interleaving banks) (2 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 8, cas latency = 2 a0 - a9 cby read command bank b read command bank a bx0 bx1 bx2 bx3 bx4 bx5 bx6 bx7 by0 by1 t ck2 high t rcd t ac2 t rp cax precharge command bank b ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 activate command bank b rbx rbx activate command bank a rax rax cbx read command bank b activate command bank b rby rby
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 47 clk cke cs dq ras cas we a11(bs) dqm 18. 3 random row read (interleaving banks) (3 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 8, cas latency = 3 a0 - a9 cby read command bank b by0 t ck3 high t ac3 activate command bank b rbx rbx activate command bank a rax rax cbx read command bank b activate command bank b rby rby t rcd precharge command bank b cax read command bank a t rp bx0 bx1 bx2 bx3 bx4 bx5 bx6 bx7 ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 precharge command bank a
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 48 clk cke cs dq ras cas we a11(bs) dqm 19.1 random row write (interleaving banks) (1 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 8, cas latency = 1 a0 - a9 t ck1 high cax rax rax write command bank a t rcd activate command bank a cbx rbx rbx write command bank b activate command bank b ray ray precharge command bank a activate command bank a t rp precharge command bank b write command bank a cay dax0 dax3 dax2 dax1 dax4 dax7 dax6 dax5 dbx0 dbx3 dbx2 dbx1 dbx4 dbx7 dbx6 dbx5 day0 day3 day2 day1 t dpl
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 49 clk cke cs dq ras cas we a11(bs) dqm 19.2 random row write (interleaving banks) (2 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 8, cas latency = 2 a0 - a9 t ck2 high t rcd t rp write command bank a cay dax0 dax3 dax2 dax1 dax4 dax7 dax6 dax5 dbx0 dbx3 dbx2 dbx1 dbx4 dbx7 dbx6 dbx5 day0 day3 day2 day1 t dpl write command bank a cax activate command bank a rax rax activate command bank b rbx rbx cbx precharge command bank a write command bank b activate command bank a ray ray cay precharge command bank b write command bank a day4 t dpl
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 50 clk cke cs dq ras cas we a11(bs) dqm 19.3 random row write (interleaving banks) (3 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 8, cas latency = 3 a0 - a9 t ck3 high dax0 dax3 dax2 dax1 dax4 dax7 dax6 dax5 dbx0 dbx3 dbx2 dbx1 dbx4 dbx7 dbx6 dbx5 day2 day1 day0 write command bank a cax activate command bank a rax rax activate command bank b rbx rbx activate command bank a ray ray day3 t dpl cbx write command bank b precharge command bank a write command bank a cay precharge command bank b t rp t dpl t rcd
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 51 \ clk cke cs dq ras cas we ba dqm 17.2 random column write (page within same bank) (2 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap burst length = 4, cas latency = 2 addr cbx write command bank b cby write command bank b precharge command bank b dbw0 dbw3 dbw2 dbw1 dbx1 dbx0 dby0 dby3 dby2 dby1 dbz0 dbz3 dbz2 dbz1 t ck2 activate command bank b cax write command bank b raw raw activate command bank b cbz write command bank b rbz rbz activate command bank b cbz write command bank b rbz rbz
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 52 \ clk cke cs dq ras cas we ba dqm 17.3 random column write (page within same bank) (3 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap burst length = 4, cas latency = 3 addr cbx write command bank b cby write command bank b precharge command bank b dbw0 dbw3 dbw2 dbw1 dbx1 dbx0 dby0 dby3 dby2 dby1 dbz0 dbz1 t ck3 activate command bank b cbz write command bank b rbz rbz activate command bank b cbz write command bank b rbz rbz
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 53 \ clk cke cs dq ras cas we ba dqm 20.1 full page read cycle (1 of 3) t2 t3 t4 t0 t1 t t tt t t t tt t tttt tt tt hi-z ap burst length = full page, cas latency = 1 addr t ck1 rbx rax rbx cax rax high read command bank a activate command bank a activate command bank b ax ax+1 ax-1 ax-2 ax+2 ax bx bx+1 bx+5 bx+4 bx+3 bx+2 bx+7 bx+6 cbx read command bank b rby rby precharge command bank b activate command bank b burst stop command full page burst operation does not terminate when the burst length is satisfied; ax+1 t rp t rrd the burst counter increments and continues the burst counter wraps from the highest order page address back to zero during this time interval. bursting beginning with the starting address.
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 54 \ clk cke cs dq ras cas we ba dqm 20.2 full page read cycle (2 of 3) t2 t3 t4 t0 t1 t6 t tt t5 t t tt t tttt tt tt hi-z ap burst length = full page, cas latency = 2 addr t ck2 high ax ax+1 ax-1 ax-2 ax+2 ax bx bx+1 bx+5 bx+4 bx+3 bx+2 ax+1 bx+6 cbx read command bank b precharge command bank b burst stop command cax read command bank a activate command bank a rax rax activate command bank b rbx rbx activate command bank b rby rby t rp full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues the burst counter wraps from the highest order page address back to zero during this time interval. bursting beginning with the starting address.
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 55 \ clk cke cs dq ras cas we ba dqm 20.3 full page read cycle (3 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t t5 t t tt t tttt tt tt hi-z ap burst length = full page, cas latency = 3 addr t ck3 high ax ax+1 ax-1 ax-2 ax+2 ax bx bx+1 bx+5 bx+4 bx+3 bx+2 ax+1 cbx read command bank b precharge command bank b burst stop command cax read command bank a activate command bank a rax rax activate command bank b rbx rbx activate command bank b rby rby t rrd full page burst operation does not the burst counter wraps from the highest order page address back to zero durin g this time interval. terminate when the length is satisfied; the burst counter increments and continues bursting beginning with the starting address.
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 56 \ clk cke cs dq ras cas we ba dqm 21.1 full page write cycle (1 of 3) t2 t3 t4 t0 t1 t t tt t t t tt t tttt tt tt hi-z ap burst length = full page, cas latency = 1 addr t ck1 rbx rax rbx cax rax high write command bank a activate command bank a activate command bank b dax dax+1 dax-1 dax+2 dax+2 dax dbx dbx+1 cbx write command bank b rby rby precharge command bank b activate command bank b burst stop command dax+1 page length: 2mb x 4i/o x 2 banks = 1024 1mb x 8i/o x 2 banks = 512 512kb x 16i/o x 2 banks = 256 data is ignored. dbx+3 dbx+2 dbx+4 dbx+5 dbx+6 dbx+7 full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues the burst counter wraps from the highest order page address back to zero during this time interval. bursting beginning with the starting address.
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 57 \ clk cke cs dq ras cas we ba dqm 21.2 full page write cycle (2 of 3) t2 t3 t4 t0 t1 t t tt t5 t t tt t tttt tt tt hi-z ap burst length = full page, cas latency = 2 addr t ck2 high cbx write command bank b precharge command bank b burst stop command cax write command bank a activate command bank a rax rax activate command bank b rbx rbx activate command bank b rby rby data is ignored. dax dax+1 dax-1 dax+3 dax+2 dax dbx dbx+1 dax+1 dbx+3 dbx+2 dbx+4 dbx+5 dbx+6 full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues the burst counter wraps from the highest order page address back to zero during this time interval. burstin g be g innin g with the startin g address.
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 58 \ clk cke cs dq ras cas we ba dqm 21.3 full page write cycle (3 of 3) t2 t3 t4 t0 t1 t6 t tt t5 t t tt t tttt tt tt hi-z ap burst length = full page, cas latency = 3 addr t ck3 high cbx write command bank b precharge command bank b burst stop command cax write command bank a activate command bank a rax rax activate command bank b rbx rbx activate command bank b rby rby dax dax+1 dax-1 dax+3 dax+2 dax dbx dbx+1 dax+1 dbx+3 dbx+2 dbx+4 dbx+5 full page burst operation does not the burst counter wraps from the highest order page address back to zero during this time interval. terminate when the length is satisfied; the burst counter increments and continues bursting beginning with the starting address. data is ignored.
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 59 \ clk cke cs dq ras cas we ba dqm 22.1 precharge termination of a burst (1 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap bu r st length = full page, c a s latency = 1 addr t ck1 rax rax cax write command b a n k a activate command bank a precharge command bank a dax0 dax4 dax3 dax2 dax1 precharge termination of a write burst. write data is masked. ray ray cay activate command bank a read command bank a ay0 ay1 ay2 precharge termination of a read burst. precharge command bank a activate command b a n k a write command bank a daz0 daz3 daz2 daz1 t rp t rp daz4 daz7 daz6 daz5 raz raz caz
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 60 \ clk cke cs dq ras cas we ba dqm 22.2 precharge termination of a burst (2 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap bu r st length = 8 o r full page, cas latency = 2 addr t ck2 precharge command bank a dax0 dax3 dax2 dax1 precharge termination of a write burst. write data is masked. ay0 ay1 ay2 precharge termination of a read burst. precharge command bank a t rp activate command bank a rax rax write command bank a cax cay read command bank a high activate command bank a ray ray t rp activate command bank a raz raz caz read command bank a az0 az1 az2 precharge command bank a t rp
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 61 \ clk cke cs dq ras cas we ba dqm 22.3 precharge termination of a burst (3 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap bu r st length = 4,8 o r full page, c a s latency = 3 addr t ck3 precharge command bank a dax0 precharge termination of a write burst. write data is masked ay0 ay1 ay2 precharge termination precharge command bank a t rp activate command bank a rax rax write command bank a cax cay read command bank a high activate command bank a ray ray t rp activate command bank a raz raz of a read burst.
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 62 complete list of operation commands sdram function truth table current state 1 cs ras cas we bs addr action idle h l l l l l l l x h h h l l l l x h h l h h l l x h l x h l h l x x bs bs bs bs x op- x x x x ra ap x code nop or power down nop illegal 2 illegal 2 row (&bank) active; latch row address nop 4 auto-refresh or self-refresh 5 mode reg. access 5 row active h l l l l l l x h h h l l l x h l l h h l x x h l h l x x x bs bs bs bs x x x ca,ap ca,ap x ap x nop nop begin read; latch ca; determine ap begin write; latch ca; determine ap illegal 2 precharge illegal read h l l l l l l l x h h h h l l l x h h l l h h l x h l h l h l x x x bs bs bs bs bs x x x x ca,ap ca,ap x ap x nop (continue burst to end;>row active) nop (continue burst to end;>row active) burst stop command > row active term burst, new read, determine ap 3 term burst, start write, determineap 3 illegal 2 term burst, precharge illegal write h l l l l l l l x h h h h l l l x h h l l h h l x h l h l h l x x x bs bs bs bs bs x x x x ca,ap ca,ap x ap x nop (continue burst to end;>row active) nop (continue burst to end;>row active) burst stop command > row active term burst, start read, determine ap 3 term burst, new write, determineap 3 illegal 2 term burst, precharge 3 illegal read with auto precharge h l l l l l l l x h h h h l l l x h h l l h h l x h l h l h l x x x bs bs x bs bs x x x x x x x ap x nop (continue burst to end;> precharge) nop (continue burst to end;> precharge) illegal 2 illegal 2 illegal illegal 2 illegal 2 illegal
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 63 sdram function truth table(continued) current state 1 cs ras cas we bs addr action write with auto precharge h l l l l l l l x h h h h l l l x h h l l h h l x h l h l h l x x x bs bs x bs bs x x x x x x x ap x nop (continue burst to end;> precharge) nop (continue burst to end;> precharge) illegal 2 illegal 2 illegal illegal 2 illegal 2 illegal precharging h l l l l l l x h h h l l l x h h l h h l x h l x h l x x x bs bs bs bs x x x x x x ap x nop;> idle after trp nop;> idle after trp illegal 2 illegal 2 illegal 2 nop 4 illegal row activating h l l l l l l x h h h l l l x h h l h h l x h l x h l x x x bs bs bs bs x x x x x x ap x nop;> row active after trcd nop;> row active after trcd illegal 2 illegal 2 illegal 2 illegal 2 illegal write recovering h l l l l l l x h h h l l l x h h l h h l x h l x h l x x x bs bs bs bs x x x x x x ap x nop nop illegal 2 illegal 2 illegal 2 illegal 2 illegal refreshing h l l l l x h h l l x h l h l x x x x x x x x x x x x x x x nop;> idle after trc nop;> idle after trc illegal illegal illegal mode register accessing h l l l l x h h h l x h h l x x h l x x x x x x x x x x x x nop nop illegal illegal illegal
hyb39s16400/800/160bt-8/-10 16mbit synchronous dram semiconductor group 64 clock enable (cke) truth table: abbreviations: ra = row address bs = bank address ca = column address ap = auto precharge notes for sdram function truth table : 1. current state is state of the bank determined by bs. all entries assume that cke was active (high) during the prece d ing clock cycle. 2. illegal to bank in specified state; function may be legal in the bank indicated by bs, depending on the state of that bank. 3. must satisfy bus contention, bus turn around, and/or write recovery requirements. 4. nop to bank precharging or in idle state. may precharge bank(s) indicated by bs (andap). 5. illegal if any bank is not idle. 6. cke low to high transition will re-enable clk and other inputs asynchronously. a minimum setup time must be satisfied befor e any command other than exit. 7. power-down and self-refresh can be entered only from the all banks idle state. 8. must be legal command as defined in the sdram function truth table. state(n) cke n-1 cke n cs ras cas we addr action self- refresh 6 h l l l l l l x h h h h h l x h l l l l x x x h h h l x x x h h l x x x x h l x x x x x x x x x x invalid exit self-refresh, idle after trc exit self-refresh, idle after trc illegal illegal illegal nop (maintain self-refresh) power-down h l l l l l l x h h h h h l x h l l l l x x x h h h l x x x h h l x x x x h l x x x x x x x x x x invalid exit power-down, > idle. exit power-down, > idle. illegal illegal illegal nop (maintain low-power mode) all. banks idle 7 h h h h h h h h l h l l l l l l l l x h l l l l l l x x x h h h l l l x x x h h l h l l x x x h l x x h l x x x x x x x x x x refer to the function truth table enter power- down enter power- down illegal illegal illegal enter self-refresh illegal nop any state other than listed above h h l l h l h l x x x x x x x x x x x x x x x x x x x x refer to the function truth table begin clock suspend next cycle 8 exit clock suspend next cycle 8 . maintain clock suspend.

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